1. Field of Invention
The present invention relates to analog-to-digital (A/D) converters and more particularly to a charge redistribution A/D converter in which the resolution of the converter may be extended without appreciably increasing the area occupied by the A/D converter on an integrated circuit chip.
2. State of the Art
Successive approximation A/D converters are well-known in the art. In general terms, such A/D converters use a collection of binary-weighted capacitors, resistors or some combination thereof successively switched into and/or out of the circuit so as to compare an unknown analog input voltage with binary-weighted fractions of a reference voltage. To form a collection of binary-weighted capacitors or resistors on an integrated circuit chip, typically an array of unit capacitors or unit resistors each having some specified minimum size is formed, after which the unit capacitors or unit resistors are suitably interconnected to form a collection of binary-weighted capacitors or resistors. The unit capacitor or unit resistor size is chosen in order to meet the accuracy requirements of the A/D converter in the face of process variations. For example, a unit capacitor is typically formed by a nominally square area of metal or polysilicon deposited on an integrated circuit wafer. Because of process imperfections, however, the edges of the metal or polysilicon area may, instead of being perfectly straight, exhibit some waviness, such that the actual capacitance of the unit capacitor will vary somewhat from the design value.
In a typical charge-redistribution A/D converter using a collection of binary-weighted capacitors, a least-significant bit of digital output is produced using a capacitor formed from a single unit capacitor, and the most-significant bit is produced using a capacitor formed from 2.sup.n-1 interconnected unit capacitors where n is the resolution, or number of output bits, of the A/D converter. Mathematically it may be shown that, to meet the accuracy requirements of the converter (viz., the digital output accurately reflecting the analog input to within .+-.1/2 LSB), the capacitor used to produce the least-significant bit may have a tolerance of 50%, the capacitor used to produce the next-significant bit must have a tolerance of 25%, and so forth, such that the capacitor used to produce the most-significant bit is required to have a tolerance of 100/2.sup.n %. For a 12-bit converter (n=12), the capacitor used to produce the most-significant bit must have a tolerance of 0.02%. Given a particular process, this strict tolerance imposes a severe limit on process variations as well as a minimum limit on the size of the unit capacitors. That is to say, if the unit capacitor is made very small, the variation in area (capacitance) produced by the waviness of the edge of the metal square will be greater than if the unit capacitor is made larger.
For every additional bit of resolution desired from the A/D converter, the number of unit capacitors must be doubled, substantially doubling the size of the A/D converter. The size penalty incurred to achieve higher resolution is therefor severe. What is needed is a way to increase the resolution of the A/D converter with a minimum increase in size while maintaining the required accuracy of the converter.